1. Field of the Invention
The present invention relates generally to cardiac pacemakers. In particular, the present invention is a dual chamber pacemaker having a control system including a programmable microprocessor and a hardware state machine which operate independently and in synchronization with one another.
2. Description of the Related Art
Dual chamber cardiac pacemakers are in widespread use and disclosed generally in the following U.S. Patents:
Dual chamber brady (bradycardia) pacemakers have the ability to sense and pace both the atrium and ventricle of the patient""s heart. Accordingly, sensed events (i.e., cardiac-induced electrical stimuli) are monitored during both the sequential and repeating atrial and ventricular cardiac cycles. Pacing pulses (i.e., a paced event) can be generated at the end of each cardiac cycle. Whether or not a pacing pulse is generated during each cycle depends upon a number of factors including whether or not a sensed event occurred during the cycle, and if so, the time within the cycle that the sensed event occurred. The pacemaker includes a control system for monitoring the sensed events and controlling the generation of pacing pulses in accordance with a predetermined operating mode.
Pacemakers of these types are typically configured to operate in one of a variety of modes. Commonly used operating modes include DDD (dual-chamber pacing, dual-chamber sensing, dual mode triggered), DDDR (dual-chamber pacing, dual-chamber sensing, dual mode triggered, rate-responsive), DDI (dual-chamber pacing, dual-chamber sensing, dual mode inhibited), and DDIR (dual-chamber pacing, dual-chamber sensing, dual mode inhibited, rate-responsive).
When operating in most, if not all of these dual chamber modes, the control system will make use of time periods known as the atrioventricular interval (AVI) and the ventriculoatrial interval (VAI). Briefly, the AVI is a programmed value representing the desired longest interval from a paced or sensed atrial cycle event to the next paced or sensed ventricular event. In other words, if a sensed ventricular event is not detected within the AVI following the beginning of an atrial cycle, a ventricular pacing pulse will be produced at the expiration of the AVI. Similarly, the VAI is a programmed value representing the desired longest interval from a paced or sensed ventricular cycle event to the next paced or sensed atrial event. If a sensed atrial event is not detected within the VAI following the beginning of a ventricular cycle, an atrial pacing pulse will be produced at the expiration of the VAI.
Electronic control systems for dual chamber pacemakers are described in the above-identified patents as well as in Chapter 10, Design of Cardiac Pacemakers. In general, the control systems of dual chamber pacemakers are implemented by using programmed microprocessors and/or hardware logic circuits (also known as state machines). Pacemakers with microprocessor-based control systems are flexible in that they can be programmed to operate in a number of different modes. The selected operational mode can also be quickly and easily changed. In view of the nature of the software design process, microprocessor-based control systems also can be relatively efficiently designed and implemented. However, they consume relatively large amounts of power, thereby limiting the implanted device lifetime. Relatively small but undeterminable latencies (delays) in the program code execution are also inherent in microprocessor-based control systems. Because of these inherent delays, the initiation of pacing pulses and other responses by the pacemaker to sensed cardiac events and timed intervals can be either premature or latent. The result this random indeterminacy of exactly when the pacing pulses will be delivered from a microprocessor-based pacemaker is commonly referred to as jitter.
Hardware state machine control systems generally have lower power requirements than microprocessors and can therefore operate for longer periods of time. Hardware state machine control systems are also relatively deterministic and are not subject to the latencies and jitter problems present in microprocessor-based devices. However, hardware state machine control systems can be relatively inefficient to design and debug. State machine control systems are also relatively inflexible. Unlike microprocessor-based control systems, hardware state machines are generally incapable of operating in different modes or of changing their programmable operation on the fly.
There remains a continuing need for improved pacemaker control systems. In particular, there is a need for a relatively deterministic and jitter-free pacemaker that can be efficiently designed and implemented. A control system of this type which is capable of operating in different modes and capable of having its operation changed on the fly would be especially desirable. Commercial viability would be enhanced if the control system had relatively low power requirements.
The present invention is a deterministic and jitter-free dual chamber medical device such as a brady pacemaker which can be efficiently designed and implemented. The control system of the pacemaker can be programmed to operate in a number of different operating modes, and is capable of dynamically adapting to changing situations.
In one embodiment, the device includes at least one sense terminal for receiving signals representative of atrial and ventricular sensed events, and pacing circuitry for generating atrial and ventricular pacing pulses in response to pacing commands. The device also includes a common memory for storing data representative of atrial and ventricular events, at least one common timer, a hardware state machine and a programmed microprocessor. The hardware state machine is connected to the at least one sense terminal, the pacing circuitry, the at least one common memory and the common timer. The state machine generates the pacing commands in response to timeouts of the at least one common timer and causes data representative of atrial and ventricular sensed events and atrial and ventricular paced events associated with the pacing commands to be stored in the common memory. The microprocessor is connected to the common memory and the at least one common timer. The microprocessor evaluates the atrial and ventricular events stored in the common memory and loads the at least one common timer with escape interval values representative of a period during which a next pacing event is expected to occur.
One embodiment of the device includes a single common common timer. Also included in this embodiment is a chamber memory location in the common memory for storing data representative of a chamber in which the next pacing event is expected to occur. The microprocessor causes data representative of the chamber in which the next pacing event is expected to occur to be stored in the chamber memory location.
Another embodiment of the device includes an atrial timer for timing atrial events and a separate ventricular timer for timing ventricular events. The hardware state machine generates atrial pacing commands in response to timeouts of the atrial timer and ventricular pacing commands in response to timeouts of the ventricular timer. An advantage of the dual-timer embodiment is that the timer for the chamber that is not expected to have the next sensed event can serve as a trigger to perform a mode switching function for the device.
Yet another embodiment includes a real time clock connected to the microprocessor. The hardware state machine causes time of occurrence data representative of the time of atrial and ventricular sensed events and paced events to be stored in the common memory. The microprocessor determines the escape interval values as a function of the time of occurrence of the atrial and ventricular sensed events and a delay period between the time of occurrence and a then-current time, to compensate for microprocessor-induced latencies.
In another embodiment the microprocessor is programmed to operate in an active mode and load the at least one common timer with the escape interval values in response to wakeup commands, and to operate in an inactive mode after loading the at least one common timer. The hardware state machine issues wakeup commands to the microprocessor in response to timeouts of the at least one common timer and in response to sensed atrial and ventricular events.